AI Chips Technology Trends & Landscape (GPU + TPU + FPGA + Startups)

Nvidia GPU

Image source: Nvidia
Modified from Nvidia source
Source

Google TPU

TPU Block Diagram

Intel FPGA

Source (Intel)
Source (Tensor block)
Source (Groups of layers to be processed in the pipeline concept)
Source (Process the 3rd and 2nd last layers)
Source

Xilinx ACAP

Source
Xilinx Versal

Flexibility and Generalization

Dataflow v.s. Instruction Flow (Optional)

Source
Source

DL Architecture

  • can utilize distributed memory in
  • a pipeline structure.
Source: Wikipedia (Instruction executions are overlapped with a 5-stage pipeline.)
Source (for illustration only)

Graphcore

Source
Source
Source

Cerebras

Source: Cerebras
Source: Cerebras
Source
Source
Source
Source
Source
Source
Source
Source
Source

Groq

Source

Mythic

Source
  • Compute-in-memory,
  • Dataflow architecture and
  • Analog computing.
Source
Source
Source

Hailo

Source
Source

More …

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